From Single Floor to Skyscraper: Vertical Stacking in the Sub-3nm Era

In the world of semiconductors, the need for higher performance and greater efficiency has driven engineers to push beyond traditional design. The rapid approach of sub-3nm era, has driven an innovative solution: vertical stacking. This technique in chip design and assembly can be likened to building skyscrapers instead of single-story homes, a transformation that reshapes the landscape of semiconductor technology forever.

For decades, Moore's Law predicted the doubling of performance at same cost with an increase in the number of transistors on a chip. However, as the industry approaches sub-3nm technology, this law is reaching its physical limits. Engineers have encountered significant challenges in squeezing more transistors into limited 2D space. Enter vertical stacking, where instead of spreading components horizontally, they are layered on top of each other, allowing more components to be packed into a smaller 2-D footprint.

Vertical stacking leverages the Z-axis, which adds a new dimension to semiconductor architecture. By stacking layers of transistors and other components on top of each other, engineers can create smaller chips with vertical pathways for electrical signals. This method significantly enhances computational speed while reducing energy consumption—benefits critical to advancing technologies like artificial intelligence, augmented reality, and real-time data processing.

While the idea of vertical stacking isn’t new, its implementation at the sub-3nm level is transformative. Back in 2015, Stanford engineers demonstrated the concept with skyscraper-style chip designs that could improve performance by a thousand-fold. Today, the industry is realizing these possibilities with ultra-thin devices that offer unprecedented processing power in ever-smaller form factors. Imagine a smartwatch that is five times thinner but one hundred times more powerful—this is the promise of vertical stacking in the sub-3nm era​.

Although vertical stacking offers significant advantages, it also presents complex engineering challenges. One of the primary concerns is power delivery. Every layer in a vertically stacked chip requires a stable and efficient power supply, a task that becomes more difficult as chips become more densely packed. Ensuring that each layer receives adequate power without causing overheating is a delicate balancing act.

Through-Silicon Vias (TSVs), which are tiny vertical conduits that carry power and signals between stacked layers, are the key to overcoming these challenges. However, TSVs come with their own set of issues, particularly in the sub-3nm space. Electromigration, where the movement of atoms due to high current density can cause failures in the chip, is a common problem in smaller TSVs. Addressing these challenges requires sophisticated design strategies and material innovations​.
Another critical challenge is signal integrity.

As components are stacked closer together, the risk of electromagnetic interference, or crosstalk, increases. This can degrade signal quality and affect the performance of high-speed applications. Advanced design techniques, including the strategic placement of signal and ground vias and the use of shielding, help mitigate these risks. Engineers also employ dummy metal fill and use full-wave 3D modelling techniques to optimise TSV placement and design, minimizing signal degradation​.

Testing vertically stacked chips is another area that demands innovation. Traditional methods of testing rely on direct access to input/output (I/O) points, which becomes increasingly difficult with vertical architectures. With limited physical access to individual layers, new approaches are required to ensure each component functions correctly. Engineers have developed special test circuits integrated into each layer, allowing them to probe the chip's functionality even when physical access is restricted.

Thermal management is also a key concern in vertically stacked chips. As layers are stacked, heat dissipation becomes more complex, and overheating can lead to performance issues and potential chip failures. Advanced cooling techniques and materials are being explored to keep these high-density chips operating at optimal temperatures​.

Companies like Intel, TSMC and Samsung have invested in 3-D transistor architecture, such as Intel’s RibbonFET and Samsung’s Gate-All-Around (GAA) transistors. These advancements are laying the foundation for complementary FETs (CFETs) and vertical nanowires, which will further improve performance and energy efficiency​.

The impact of these innovations is already being felt across various industries. Ultra-thin devices, from laptops to smartwatches, are becoming more powerful, energy-efficient, and capable of handling complex tasks that were once the domain of larger, more power-hungry machines. Industries ranging from healthcare to automotive are also set to benefit from the improved capabilities of vertically stacked semiconductors​.

A New Era for Chip Design

Companies like Quest Global are building Centers of Competency to deliver the skills needed by the industry to navigate the complexities of sub-3nm chip technology. Quest Global’s recognition as a trusted partner in helping clients overcome the challenges of vertical stacking will play a pivotal role in extending the legacy of Moore’s Law and shaping the future of computing​.

In conclusion, vertical stacking in the sub-3nm era is more than just a technological advancement—it’s a paradigm shift for chip designers. 

Disclaimer: Taher Madraswala is the Strategic Client Partner - India, Quest Global. The views expressed in this article are purely those of the author.